1. Technical Field
The present inventions relate to integrated circuit chips and, more particularly, to chips in which the components of loops, such as delay locked loops, are distributed amongst more than one chip.
2. Background Art
Controllable delay lines are often controlled through a phase detector used to compare the phase of the output of the delay line against some reference, and some sort of delay controller to process the output of the phase detector and adjust the delay of the controllable delay line accordingly.
Traditional controllable delay lines are controlled via some internal, on die mechanism, digital or analog, using control and signal processing blocks that may consume relatively large amounts of area or power. This can be especially problematic in devices where area and power are under severe constraints, for example DRAM (dynamic random access memory) chips.
FIG. 1 illustrates a prior art chip 2 that includes delay locked loop (DLL) 6. DLL 6 includes a controllable delay line 8, a phase detector 10, and a delay controller 12. Controllable delay line 8 provides a controllable delay to an input signal (such as a clock input signal) from receiver 4 to provide an output signal (such as a clock output signal) that has a particular phase relationship to the input signal. Phase detector 10 receives the input and output signals and provides to delay controller 12 a phase difference indicating signal (sometimes called an error signal) that is indicative of a phase delay between the input and output signals. In response to the phase difference indicating signal, delay controller 12 provides a delay control signal to controllable delay line 8 to control delay of the input signal.
In some prior art systems, a capacitor of an analog loop filter has have been put as a discrete component off the chip onto a circuit board. For example, if delay controller 12 includes an analog loop filter, a capacitor of the loop filter might be put as a discrete component off the chip onto a circuit board that supports chip 2.
The desired phase difference between the clock input signal and the clock output signal may be zero degrees or some other amount such as 90 or 180 degrees. There may be various taps off of delay line 8 that provide signals have different phase relationships with the input signal.
There are numerous ways to implement DLLs. For example, in some DLLs, phase detector 10 merely detects whether the phase of the output signal is ahead of or behind the phase of the input signal and provides a binary signal to delay controller 12 in response thereto. Note that being more than half a cycle ahead is the same as being behind and being more than half a cycle behind is the same as being ahead. In other DLLs, phase detector 10 detects an amount of phase difference between the output signal and provides a signal that is related (for example, proportional) to the phase difference to delay controller 12. Various other details exist. The controllable delay lines and delay controller may be digital or analog. Charge pumps, low pass filters, digital signal processors (DSPs), DSP filters, and finite state machines (FSMs) may be used.